The present invention relates to a video reproduction system, and more particularly, to a reproduction error correction circuit for a video reproduction system and the method therefor.
FIG. 1 is a block diagram of the reproduction error correction circuit for a conventional video reproduction system. In FIG. 1 the reproduction error correction circuit comprises a time base error correction unit 10 composed of an analog-to-digital (A/D) converter 100 and a first-in-first-out (FIFO) memory 101, and a drop-out compensation unit 20 composed of a one horizontal line (1H) delay 102 and a chromatic signal phase corrector 103.
The horizontal synchronization signal of an input video signal, or a clock signal phase-synchronized with a color burst signal, is applied both as a sampling clock input to the A/D converter 100 and a write clock (WCK) input to the FIFO memory 101 for time base correction. A read clock input (RCK) is applied to the FIFO memory 101, which read clock input (RCK) usually is supplied from a crystal oscillator. Minor time base errors are removed by writing into the FIFO memory 101 with the sampling clock signal being phase-synchronized with the input video signal and by reading with the read clock which has a very stable frequency. The average rate of the write clock (WCK) input taken over several scan lines is controlled to be the same as the average rate of the read clock input (RCK) over the same time period; in video tape machines this is customarily arranged for by controlling the speed of a capstan regulating the spooling of video tape between pay-out and take-up reels.
When a drop-out is generated, the drop-out correction unit 20 basically compensates the drop-out by replacing the present signal with signal from the immediately preceding scan line. Therefore, a delay circuit 102 is required for delaying the present signal by one horizontal scanning period, or providing 1H delay, so the present signal is available to compensate for drop-out occurring during the next scan line. Commonly, this delay circuit 102 is provided by a further line-storage memory, in addition to the line-storage memory used for time-base correction. In other words, the reproduction error correction circuit for a conventional video reproduction system uses both a FIFO memory and a 1H delay line, each of which takes up considerable area on an integrated-circuit die and consumes an appreciable amount of electrical power. The consumption of electrical power increases the amount of heat that must be dissipated from the integrated circuit in order not to overheat its components.